Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Absolute Maximum Ratings
- Power Supply DC Characteristics
- LVCMOS DC Characteristics
- Differential DC Characteristics
- AC Characteristics
- Additive Phase Jitter
- Parameter Measurment Information
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Recommendations for Unused Input and Output Pins
- Differential Clock Input Interface
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
1
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS83023I is a dual, 1-to-1 Differential-to-
LVCMOS Translator/Fanout Buffer and a mem-
ber of the HiPerClockSTM family of High Perfor-
mance Clock Solutions from ICS. The differen-
tial inputs can accept most differential signal
types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and
translate into two single-ended LVCMOS outputs. The small
8-lead SOIC footprint makes this device ideal for use in ap-
plications with limited board space.
Features
Two LVCMOS / LVTTL outputs
Two differential CLKx, nCLKx input pairs
CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency: 350MHz (typical)
Output skew: 60ps (maximum)
Part-to-part skew: 500ps (maximum)
Additive phase jitter, RMS: 0.14ps (typical)
Small 8 lead SOIC package saves board space
3.3V operating supply
-40C to 85C ambient operating temperature
Available in both standard and lead-free RoHS-compliant
packages
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS83023I
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
CLK0
nCLK0
nCLK1
CLK1
1
2
3
4
HiPerClockSTM
ICS
V
DD
Q0
Q1
GND
8
7
6
5
Q0
CLK0
nCLK0
Q1
CLK1
nCLK1
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
2
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
3
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= 3.3V0.3V, T
A
= -40C
TO
85C
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AXIMUM
R
ATINGS
Supply Voltage, V
DD
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Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DD
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Package Thermal Impedance,
JA
112.7C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the
DC Characteristics
or
AC
Characteristics
is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
4
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
T
ABLE
4. AC C
HARACTERISTICS
,
V
DD
= 3.3V0.3V, T
A
= -40C
TO
85C
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83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
5
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
A
DDITIVE
P
HASE
J
ITTER
Additive Phase Jitter
@ 100MHz
(12kHz to 20MHz)
= 0.14ps typical
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the
dBc Phase Noise.
This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
As with most timing specifications, phase noise measure-
ments have issues. The primary issue relates to the limita-
tions of the equipment. Often the noise floor of the equipment
is higher than the noise floor of the device. This is illustrated
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a
dBc
value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
above. The device meets the noise floor of what is shown, but
can actually be lower. The phase noise is dependant on the
input source and measurement equipment.
O
FFSET
F
ROM
C
ARRIER
F
REQUENCY
(H
Z
)
SSB P
HASE
N
OISE
dB
c/H
Z
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
6
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
Clock
Outputs
0.8V
2V
2V
0.8V
t
R
t
F
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
CMR
Cross Points
V
PP
GND
CLK
nCLK
V
DD
t
sk(pp)
V
DD
2
V
DD
2
Qx
Qy
PART 1
PART 2
nCLK0, nCLK1
CLK0, CLK1
Q0, Q1
t
PD
V
DD
2
-1.65V 0.15V
1.65V 0.15V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
t
PERIOD
t
PW
t
PERIOD
odc =
V
DD
2
x 100%
t
PW
Q0, Q1
GND
D
IFFERENTIAL
I
NPUT
L
EVEL
V
DD
t
sk(o)
V
DD
2
V
DD
2
Qx
Qy
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
7
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
A
PPLICATION
I
NFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V and V
DD
= 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
I
NPUTS
:
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from
CLK to ground.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
8
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
F
IGURE
2C. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2B. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
2D. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL,
HCSL and other differential signals. Both V
SWING
and V
OH
must
meet the V
PP
and V
CMR
input requirements. Figures 2A to 2E
show interface examples for the HiPerClockS CLK/nCLK in-
put driven by the most common driver types. The input inter-
F
IGURE
2A. H
I
P
ER
C
LOCK
S CLK/nCLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
faces suggested here are examples only. Please consult with
the vendor of the driver component to confirm the driver termi-
nation requirements. For example in
Figure 2A,
the input ter-
mination applies for ICS HiPerClockS LVHSTL drivers. If you
are using an LVHSTL driver from another vendor, use their
termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
F
IGURE
2E. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
WITH
AC C
OUPLE
Zo = 50 Ohm
R3
125
HiPerClockS
CLK
nCLK
3.3V
R5
100 - 200
3.3V
R2
84
3.3V
R6
100 - 200
Input
R5,R6 locate near the driver pin.
Zo = 50 Ohm
R1
84
R4
125
C2
LVPECL
C1
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
9
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
T
RANSISTOR
C
OUNT
The transistor count for ICS83023I is: 416
Pin-to-pin compatible with MC100EPT23
T
ABLE
5.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
8 L
EAD
SOIC
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
153.3C/W
128.5C/W
115.5C/W
Multi-Layer PCB, JEDEC Standard Test Boards
112.7C/W
103.3C/W
97.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
10
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
T
ABLE
6. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-012
P
ACKAGE
O
UTLINE
- S
UFFIX
M
FOR
8 L
EAD
SOIC
L
O
B
M
Y
S
s
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M
I
N
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I
X
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M
N
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A
5
3
.
1
5
7
.
1
1
A
0
1
.
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5
2
.
0
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3
3
.
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.
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.
1
0
8
83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
11
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
T
ABLE
7. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industiral applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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83023AMI
www.icst.com/products/hiperclocks.html
REV. B JANUARY 18, 2006
12
Integrated
Circuit
Systems, Inc.
ICS83023I
D
UAL
, 1-
TO
-1
D
IFFERENTIAL
-
TO
-LVCMOS T
RANSLATOR
/B
UFFER
T
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